This invention relates to dynamic logic gates.
FIG. 1 shows a typical dynamic logic gate in which MOS transistors are used.
In FIG. 1, element 1 is a logic output terminal; element 2 is a capacitor; element 3 is a precharging transistor; elements 4 are logic input terminals; element 5 is a partial logic gate where the current between its two output terminals 5a and 5b is allowed to flow or is cut off according to the status of the logic inputs; element 9 is a transistor that cuts off the current from the logic gate during the clock precharge period and conducts during other clock periods, and element 8 is a power supply.
FIG. 2 shows the circuit of FIG. 1 with the partial logic gate 5 shown in more specific detail. In FIG. 2 elements 41-45 are logic input terminals for logic inputs D.sub.1 -D.sub.5 ; elements 51-55 are transistors composing the logic gate. A current can flow between the terminals 5a and 5b when the logic inputs D.sub.1 -D.sub.5 satisfy the following equation (1). EQU D.sub.1.D.sub.2 +D.sub.3.(D.sub.4 +D.sub.5)=1 (1)
The circuit of FIGS. 1 and 2 operates in the following sequence. First, when the clock .0. is a "0", the transistor 3 is "on", and the transistor 9 is "off". In this state, current flows from the power supply 8 to the capacitor 2 through transistor 3, and the capacitor 2 voltage rises, and the state of the logic output terminal 1 becomes "1"regardless of the state of the logic inputs D.sub.1 -D.sub.5. Next, as the clock phase changes and the clock .0. becomes a "1", the transistor 3 turns "off", and the transistor 9 turns "on". In this state, if the two terminals 5a and 5b of the partial logic gate 5 are in a state which allows current to flow therebetween, the charge stored in the capacitor 2 is discharged through the two terminals 5a and 5b as well as transistor 9, and the state of the logic output terminal 1 becomes a "0". On the other hand, if the partial logic gate 5 is in a state such that the current between the two terminals 5a and 5b is cut off, a discharge path is not formed, and the state of the logic output terminal 1 remains a "1".
In other words, the logic output generates normal values only when the clock .0. is a "1", at which time the logic output Q is expressed by the following equation (2). EQU Q=D.sub.1.D.sub.2 +D.sub.3.(D.sub.4 +D.sub.5) (2)
Dynamic logic gates such as these are frequently used because of the advantage that no steady-state operating current flows, but they are operated at low power and, as the number of inputs increases, the circuit does not become too complex; whereas, in the case of an ordinary CMOS static logic gate, the circuit becomes complex.
However, there were shortcomings in that when the dynamic gates were used in a decoder or an ROM circuit, the capacitor 2 value reached several PF and the channel width was reduced in the partial logic gates. Consequently, the load driving capability decreased so as to increase the gate delay time.